This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-28 5254, filed on Sep. 19, 2001; the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, it relates to a semiconductor device suitably applied to a trench-gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor) for power control, and a method of manufacturing such a semiconductor device.
Semiconductor devices commonly used for power control include various power MOSFETs (Field Effect Transistors) and MOS type transistors such as IGBT (Insulated Gate Bipolar Transistor). In these semiconductor devices, it is desired to reduce conductive loss during the switching operation and also to attain low capacitive property as well.
One prospective solution to satisfy such requirements is xe2x80x9ctrench-gate structurexe2x80x9d.
FIG. 10 is a diagram showing a main portion of an exemplary cross-sectional structure of a test trench-gate power MOSFET that is embodied for a trial by the inventors of the present invention in the course of attempting to make the invention complete.
Specifically, the MOSFET shown in the drawing has a configuration where an n+-type semiconductor substrate 101 is superposed with an nxe2x88x92-type epitaxial semiconductor layer 2, a p-type base region 103, and an n+-type source region 104 one over another in this order. Then, trenches T are defined in such a multi-layered structure, extending perpendicular to a stacking direction of the layers, and each of the trenches has its inner wall coated with gate insulating film 107 and is further filled with polysilicon serving as a gate electrode 106. The source region 104 is selectively removed between adjacent ones of the trenches to create a recessed portion reaching the base region 103, and thereafter, an additional p+-type region 105 is selectively formed in the exposed surface of the base region.
The gate electrode 106 and the gate insulating film 107 are covered with interlayer insulating film 108 while the source region 104 has its exposed portion been in contact with source electrode 109 deposited thereover. In an underside of the substrate 101, there is a drain electrode 110.
Although only a cell segment corresponding to the single trench is depicted in FIG. 10, a device often includes a plurality of such cells in an array, each having the trench.
In the trench-gate structure as mentioned above, the device, when miniaturized having an increased number of trench-gates, meets a corresponding increase in the total channel width, and this enables its ON-resistance to be reduced.
Such a reduction of the ON-resistance in the device by virtue of a miniaturization of itself is well explained by the following background principle. In general, components of an ON-resistance in a transistor include a resistance of a high concentration substrate, a resistance of epitaxial layer, a channel resistance, a source resistance, a contact resistance, and the like. Especially, MOSFETs of low withstand voltage of 100V or below have an ON-resistance a large percentage of which is a resistance component of a channel region. For instance, approximately 20% of the total resistance is a channel resistance in a MOSFET of 100 V withstand voltage, and the value reaches as high as about 60% in a MOSFET of 30 V withstand voltage. Thus, it is considerably effective for a decrease in the ON-resistance to increase a channel density by miniaturizing the cell segment.
One deliberate solution to attain a decrease in ON-resistance in the device or a decrease in conductive loss is miniaturizing the device by reducing a pitch between cells.
On the other hand, a low capacitive property is enhanced in an improved manner of decreasing depths of both the p-type base region 3 and the trench gates.
However, an enhanced integration which is an advantageous feature of the trench-gate structure brings about the best result for the reduction of the ON-resistance but leads to an adverse effect upon a durability against breakdown, namely, xe2x80x9cavalanche tolerabilityxe2x80x9d of the device.
A definition of the term xe2x80x9cavalanche tolerabilityxe2x80x9d herein can be summed up as follows.
When the MOSFET as shown in FIG. 10 is turned off, a current path is short-circuited between a gate G and a source S to reduce a voltage VGS applied across the path between gate G and the source S down to 0 V. At this time, when VGS reaches a threshold voltage or below, a channel disappears. Since the current path is shut off, a drain current ID reaches 0 A, and this variation in current permits a load having an inductance to develop counter electromotive power which is applied to a drain D. The applied electromotive force turns a diode of the nxe2x88x92-type epitaxial layer 102 and the p-type base region 103 to reversely biased to break the device down.
The n-type source region 104, the p-type base region 103, and the n-type epitaxial layer 102 of the MOSFET constitutes a parasitic n-p-n bipolar transistor. The p-type base region 103 serving as a base of the bipolar transistor has a parasitic resistance RB. The breakdown current, which is caused as a result of turning the MOSFET off, flows into the n-type semiconductor substrate 101, the n-type epitaxial layer 102, and the p-type base region 103, respectively, and this causes the bipolar transistor to turn on. A large base resistance causes a large forward bias between the base and the emitter. In a cell(s) under an influence of such bipolar operation, a generation of heat results in positively charged electron holes being produced, and this further accelerates a heat generation. In the cell(s) suffered from such circulation, current concentratively overflows to eventually cause breakdown. This is called xe2x80x9cavalanche breakdownxe2x80x9d.
Recently, the industry has more increasingly demanded MOSFETs of more accelerated operation and higher frequency operation for applications of switching power supply, AC-DC converter, and the like. To address such demands, it is desirable that the device would not easily be broken down by surge voltage of reduced pulse width caused during the accelerated operation and/or the high frequency operation; in other words, the device should desirably have enhanced durability against avalanche breakdown.
A solution to the xe2x80x9cavalanche breakdownxe2x80x9d is a xe2x80x9ctrench contact technologyxe2x80x9d as shown in FIG. 10 where the additional p+-type region 105 is created by raising a base concentration in part of the base region 103, thereby decreasing a base resistance of the parasitic transistor (e.g., n-p-n type for the n-channel) to have a well-balanced operation.
With such a solution, however, there still arises a problem that a junction of the source region 104 with the source electrode 109, or any trench contact TC, is likely to cause ohmic malfunction due to unsteadiness of the processing, which, in turn, results in a greater liability to uneven ON-resistance.
In attempting to avoid the avalanche breakdown, it has been found that a decrease in a concentration of the source region 104 is effectual to control the parasitic transistor for a well-balanced bipolar operation.
However, this way of decreasing the concentration of the source region 104 also causes a problem that an ohmic contact with the source electrode 109 becomes further unsatisfied, which results in the ON-resistance rising.
Thus, there exist a necessity of providing a renovated trench-gate MOSFET semiconductor device that has an improved avalanche tolerability as well as a reduced ON-resistance, and a necessity, as well, of providing a method of manufacturing such a semiconductor device.
In one aspect, a semiconductor device according to the embodiment of the present invention comprises: a semiconductor layer of a first conductivity type; a semiconductor region of a second conductivity type formed on the semiconductor layer; a semiconductor region of a first conductivity type selectively provided on the semiconductor region of the second conductivity type; a trench extending from the semiconductor region of the first conductivity type through the semiconductor region of the second conductivity type to the semiconductor layer of the first conductivity type; an insulating layer provided over an inner wall of the trench; a conductor embedded in a space defined by the insulating layer in the trench; and an electrode connected to the semiconductor region of the first conductivity type,
the semiconductor region of the first conductivity type having a portion in contact with the electrode, the portion having a higher concentration of impurity of the first conductivity type than a remaining portion of the semiconductor region of the first conductivity type.
The xe2x80x9cregion higher in concentration of impurity of the first conductivity typexe2x80x9d herein is defined as a region of which impurity concentration reaches a sufficient level to permit a formation of ohmic contact with the electrode.
In another aspect, a semiconductor device according to the embodiment of the present invention comprises: a semiconductor layer of a first conductivity type; a semiconductor region of a second conductivity type formed on the semiconductor layer; a semiconductor region of a first conductivity type selectively provided on the semiconductor region of the second conductivity type; a trench extending from the semiconductor region of the first conductivity type through the semiconductor region of the second conductivity type to the semiconductor layer of the first conductivity type; an insulating layer provided over an inner wall of the trench; a conductor embedded in a space defined by the insulating layer in the trench; and an electrode connected to the semiconductor region of the first conductivity type,
the semiconductor region of the first conductivity type having a concentration distribution of the impurity of the first conductivity which is higher at a part in contact with the electrode than at a part in contact with the insulating layer.
In another aspect, a semiconductor device according to the embodiment of the present invention comprises: a semiconductor layer of a first conductivity type; a base region of a second conductivity type formed on the semiconductor layer; a source region of a first conductivity type selectively provided on the base region; a trench extending from the source region through the base region to the semiconductor layer; an gate insulating layer provided over an inner wall of the trench; a gate electrode embedded in a space defined by the gate insulating layer in the trench; and a source electrode connected to the source region,
the source region having a concentration distribution of the impurity of the first conductivity which is higher at a part in contact with the source electrode than at a part in contact with the gate insulating layer, and
the source region having a concentration distribution of the impurity of the first conductivity which is higher at the part in contact with the source electrode than at a part in contact with the base region.
A method of manufacturing a semiconductor device according to the embodiment of the present invention comprises: forming a multi-layered structure including a semiconductor layer of a first conductivity type, a semiconductor region of a second conductivity type, a semiconductor region of a first conductivity type one over another in this order; forming a trench which extends from the semiconductor region of the first conductivity type through the semiconductor region of the second conductivity type to the semiconductor layer of the first conductivity type; forming an insulating layer over an inner wall of the trench; embedding a conductor in a space defined by the insulating layer in the trench; introducing impurity of the first conductivity type into part of a surface of the semiconductor region of the first conductivity, the part being apart from the trench, so as to from a region higher in concentration of which deepest level does not reach the underlying semiconductor region of the second conductivity type, partially etching away the region higher in concentration to expose the semiconductor region of the second conductivity type; and connecting an electrode to the region higher in concentration and to the exposed portion of the semiconductor region of the second conductivity type.